Carrier transport enhancement through the use of a strained-silicon channel results in CMOS technology having improved speed and using less power than conventionally fabricated CMOS devices. Data provided by Rim et al., Characteristics and Device Designs of Sub-100 nm Strained-Si N- and PMOSFETs, VLSI Symp. Tech. Dig., pp 98–99 (2002), was measured from a PMOS structure fabricated on biaxial tensile strained silicon. Data from Thompson et al., A Logic Nanotechnology Featuring Strained Silicon, IEEE Electron Device Letter, Vol. 25, No. 4, pp. 191–193 (2004), was measured from uniaxial compressive strained PMOS.
In order to improve the hole mobility at the operating voltage, Thompson et al., supra, reported using uniaxial compressive strain on the PMOS channel along the channel direction. Unlike the hole mobility, as report4ed by Rim et al., supra, which is dependent on the operating voltage of the biaxial tensile strained PMOS, the hole mobility data gathered by Thompson et al. indicates that the hole mobility improvement is independent of the operating voltage for a uniaxial compressive strained PMOS. To achieve uniaxial compressive strain in PMOS, silicon was etched on the source/drain areas and then SiGe was selectively grown on the source/drain area. For the NMOS, high stress Si3N4 film was deposited after the gate module completion and the NMOS channel was placed under uniaxial tensile strain. The mobility improvement detected in the NMOS in this case was not as much as in the biaxial strained NMOS case. In the case of a biaxial tensile strained NMOS, the electron mobility improvement is about 80% to 100%, and has little dependence on the vertical electrical field.
We have described direct wafer bonding in publications and co-pending patent applications: Lee et al., Fabrication of Strained Silicon on Insulator (SSOI) by Direct Wafer Bonding Using Thin Relaxed SiGe Film as Virtual Substrate, MRS Proceedings Vol. 809, (2004); Maa et al., Method of making relaxed silicon-germanium on glass via layer transfer, U.S. patent application Ser. No. 10/674,369, filed Sep. 29, 2003; Maa et al., Strained silicon on insulator from film transfer and relaxation by hydrogen implantation, U.S. patent application Ser. No. 10/755,615, filed Jan. 12, 2004; Maa et al., Method of Forming Relaxed SiGe Layer, U.S. Pat. No. 6,780,796 B2, granted Aug. 24, 2004; and Maa et al., Method of Making Relaxed Silicon-Germanium on Insulator via Layer Transfer, U.S. Pat. No. 6,767,802 B1, granted Jul. 27, 2004.